Conventional data conversion devices often include an analog-to-digital converter (“ADC”).
ADCs operate primarily to quantize analog data signals for use in digital signal processing. In recent years, the need for more powerful digital signal processing systems has continued to increase, thereby requiring higher resolution and more accurate ADCs.
Conventional ADCs have commonly employed switched capacitor elements and differential amplifiers. These switched capacitor elements, in order to obtain the necessary accuracy, must be accurately matched, thereby requiring the manufacturing process to achieve high levels of accuracy, which may be difficult due to matching limitations between components. Since these limitations commonly exceed manufacturing process capabilities, various calibration techniques have been implemented.
Conventional ADCs address various ones of the above-noted disadvantages. One such conventional ADC is known as a “pipelined ADC.” A pipelined ADC operates to convert an analog signal received at the input of a pipeline of “n” stages into an “n”-bit digital output signal. Each converter stage is, essentially, a sub-ADC and a reconstructing digital-to-analog converter (“DAC”).
For instance, in a typical pipelined ADC, a “first” stage receives the analog input voltage and, in response to the analog level, converts the same to generate the most significant bit (“MSB”) of the resulting digital signal. Subsequent stages in turn refine the determination of the value of the signal, producing additional bits in less significant positions of the resulting digital signal.
More specifically, an initial “coarse” conversion of a voltage VIN is made by a nth-bit sub-ADC, which coarse conversion is a nth-bit approximation of the input voltage VIN. Commonly, a nth-bit DAC converts this nth-bit digital approximation back into an analog signal, which represents the “coarse” nth-bit approximation of the input voltage VIN. This “nth-bit” analog signal is then subtracted from the actual input voltage VIN, and the resulting remainder, or “residue,” of the first nth-bit conversion represents the residual portion of the input voltage VIN that was not accurately converted by the nth-bit sub-ADC.
This residual portion is amplified to enlarge the conversion range for a second or “finer” conversion performed by a mth-bit sub-ADC. This “finer” mth-bit digital approximation of the input voltage VIN by the mth-bit sub-ADC is passed to an adder where it is added to the “coarse” nth-bit conversion previously performed by the nth-bit sub-ADC.
This multi-stage process is repeated until the pipeline is complete, with the residue of each stage being amplified and quantized by the following stage. The limiting example of such an extension is a one-bit-per-stage architecture, which requires only one comparator per added bit of resolution desired. The gain of the inter-stage amplifier is set such that coarse and fine conversions have a one-bit overlap so as to allow for the correction of errors made in the coarse conversion.
Multi-stage pipeline ADC architectures provide a scalable approach that reduces significantly the total number of comparators required to perform a conversion. This reduction in the number of required comparators results in a significant die area and power consumption savings for the ADC.
Traditional correction logic in a pipelined ADC is implemented as “full” addition and carry over of the overlapping correction bits from each stage. Each full adder however provides for four possible states (e.g., “00,” “01,” “10,” “11”), one state more than a pipelined binary adder requires (e.g., “00,” “01,” “10”). A need therefore exists in the art for a binary adder that further increases the efficiencies of pipelined ADCs and reduces die area and power consumption requirements of the ADC. A further need exists for a three-state binary adder that eliminates the logic necessary for a “11” state in pipelined ADCs.